The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device. For example, the present invention relates to a semiconductor device including an insulated gate type field-effect transistor having a vertical transistor structure, and its manufacturing method.
The development of a CSP (Chip Size Package) type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) for lithium-ion (Li+) battery protection (EFLIP: Ecologically Flip chip MOSFET for Lithium-Ion battery Protection) has been underway from the past. As a MOSFET like this, a one-chip dual type MOSFET structure in which a drain electrode composed of a metal plate or a metal film is disposed on the back surface has been known (Japanese Unexamined Patent Application Publication No. 2008-109008 (Yoshida) and Published Japanese Translation of PCT International Publication for Patent Application, No. 2004-502293 (Kinzer et al.)).
In a semiconductor device disclosed in Yoshida, two MOSFETs are packed on one semiconductor substrate by using a common drain electrode (not shown) formed on the back surface. On the first source electrode, two first source bump electrodes connected to this first source electrode are disposed. On the second source electrode, two second source bump electrodes connected to this second source electrode are disposed.
The first source bump electrodes and the second source bump electrodes are arranged along a short side of the chip. A first gate bump electrode is disposed between the first source bump electrodes and a second gate bump electrode is disposed between the second source bump electrodes. In the MOSFET having the structure like this, a current path is formed in a direction along the short side of the chip and a current flows through the common drain electrode disposed on the back surface.
Further, in a semiconductor device disclosed in Kinzer et al., the chip is partitioned into four areas and FETs 1 and FETs 2 are alternately arranged. Each of the FET 1 and the FET 2 has a U-shape, and the FET 1 and the FET 2 are engaged with each other. The gate pads G1 and G2 of the FETs 1 and 2 are formed, within the areas of their respective FETs 1 and 2, at opposed corners of the chip.